Pipelining: Problems
Pipeline Problems
In practice RISC processors operate at more than one cycle per instruction.
The processor might occasionally stall - a result of 'data dependencies' and 'branch instructions'.
Situations that prevent starting the next logical instruction in the next clock cycle are classed as hazards of pipelining. There are three types:
Structural hazards —These happen when a required resource is busy. In our laundry analogy it might be that the place to fold and put away the laudry is a shared dorm and the lauderer's roomate has friends in and doesn't want to be disturbed until they are gone.
Data hazards—These occur when the system needs to wait for the previous instruction to complete its data read/write. In our laudry analogy that would be like finding at the folding stage, that only one of a pair of socks has been washed and dried. Before the task can be completed you have to wait for the other sock to come out from another washload.
Control hazards —These happen when a decision on control action to be taken depends on a previous instruction. In our laundry analogy we could say that how much detergent is to be used in a load is based on how clean prior load turns out.
