Pipelining Problems: Structural Hazards

Structural Hazard #1: Single Memory • Conflict for use of a resource • In MIPS pipeline with a single memory —Load/store requires memory access for data —Instruction fetch would have to stall for that cycle – Would cause a pipeline "bubble" • Solution: —separate instruction/data memories —so simulate this by having both an L1 Instruction Cache and an L1 Data Cache

Two different solutions have been used: 1) RegFile access is VERY fast: takes less than half the time of ALU stage – Write to Registers during first half of each clock cycle – Read from Registers during second half of each clock cycle 2) Build RegFile with independent read and write ports • Result: can perform Read and Write during same clock cycle