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Processing speed

Let us estimate the clock rate (frequency) of a single-cycle processor.

We know that there is 1 cycle per instruction and that lw is the most demanding instruction.

Let us assume approximate delays for major sections of the datapath:

Remember that '1 ns' is one nanosecond = 1 x 10-9s - see S.I. prefixes

2 ns delay
1 ns delay
Inst. Mem
Data Mem

Totting up these delays we find that instruction execution requires:

2 + 1 + 2 + 2 + 1 = 8 ns

frequency = 1/period

f = 1/T = 1/(8 x 10-9) = 1.25 x 108 Hz

= 125 MHz

What can we do to improve CPU performance?

We could improve clock rate - reduce the delay for each instruction being carried out, but we have to be sure that our reduction in time for each action is not too small for the task to be completed.

We could improve the architecture of the computer CPU so that steps in processing were carried out in the most efficient way - pipelining.